The magnetic random access memory (hereafter, referred to as MRAM) is a nonvolatile memory in which the number of reading/writing operations are unlimited and a low voltage operation and a high speed operation are possible. A memory cell of the MRAM includes a magnetoresistive element (exemplified by the MTJ (Magnetic Tunneling Junction) element) as an element for storing data.
As a writing method of the memory cell of the MRAM, the dual-axis writing method has been used. In the dual-axis writing method, a writing current is made flow through each of two interconnections (exemplified by a word line and a bit line) orthogonal to each other. Then, the magnetization of the magnetoresistive element of a selected memory cell (hereafter, referred to as a selected cell) is inverted by a synthetic magnetic field generated by the currents. The memory cell of the dual-axis writing type MRAM has the 1T1MTJ cell configuration. That is, the memory cell is configured by one MTJ element (1MTJ) functioning as the magnetoresistive element and one cell transistor (1T) to select the memory cell at the time of a reading operation. The area of this memory cell has a possibility that enables to ideally attain 8 F2 (F indicates the dimension of the smallest interconnection width and interconnection interval in manufacturing) and attain a cell size similar to the DRAM (Dynamic Random Access Memory). However, in the dual-axis writing method, there is a situation (hereafter, referred to as a half-selection state) in which the magnetic field is also applied to a non-selected memory cell (hereafter, referred to as a non-selected cell). For this reason, there is a defect that a writing operational margin is narrow. Also, since the typical writing current is large such as about 5 mA, it is difficult to increase the cell occupation rate and make the capacity large.
In order to solve the above problems, several techniques have been proposed. For example, by using the MRAM of the 2T1MTJ cell configuration, it is possible to solve the subject of the half-selection state, reduce the writing current to 1 mA or less and simplify peripheral circuits. Thus, the cell occupation rate can be increased similarly to the rate of the DRAM. As a result, it is suitable for attaining a larger capacity. An MRAM of the 2T1MTJ cell configuration is disclosed in, for example, Japanese Patent Application Publication JP2004-348934A (which is referred to as the patent literature 1).
FIGS. 1A and 1B are circuit diagrams showing the configuration of the MRAM cell (memory cell 200) described in the patent literature 1. As shown in FIGS. 1A and 1B, the memory cell 200 of the 2T1MTJ cell configuration is provided with one MTJ element (1MTJ) functioning as the magnetoresistive element and two cell transistors M100 and M200 (2T) to select the memory cell at the times of a writing operation and a reading operation.
The operation of the memory cell 200 of the 2T1MTJ cell configuration will be described below with reference to FIGS. 1A and 1B. At the time of the writing operation, when a word line 230 (WL) is shifted to the high level, the two transistors M100 and M200 are turned on. Together with it, a complementary voltage corresponding to a 1-bit writing information is applied to a bit line 210 (BL) and a bit line 220 (/BL). For example, when “0” is written to a selected cell, the complementary voltage of the low level (VL) is applied to the bit line 210 (BL), and the complementary voltage of the high level (VH) is applied to the bit line 220 (/BL). Similarly, when “1” is written to the selected cell, the complementary voltage of the high level is applied to the bit line 210 (BL), and the complementary voltage of the low level is applied to the bit line 220 (/BL). With those operations, as shown in FIG. 1A, a writing current IW is conducted between the transistors M100 and M200. Thus, the magnetization state of only an MTJ element 300 of the selected cell is inverted, and the 1-bit information of only the selected cell is rewritten. That is, in the case of the 2T1MTJ cell configuration, it is possible to improve the selectivity of the memory cell at the time of the writing operation.
As shown in FIG. 1B, also at the time of the reading operation, a reading current IS can be conducted to only the selected cells through the two transistors M100 and M200. In this case, when a voltage VC of about 0.3V is applied to both of the bit line 210 (BL) and the bit line 220 (/BL), the reading current IS flows through the transistors M100 and M200 of the selected cells to the MTJ element 300 whose one side terminal n30 is grounded. By detecting this current IS, it is possible to detect the resistance value of the MTJ element 300 and read the information recorded in the selected cell.
For the memory cell 200 of the 2T1MTJ configuration, it is desired to use an MTJ element 300 of three terminals, as shown in FIG. 1A. FIGS. 2 and 3 are cross-sectional views showing the structure of typical 3-terminal MTJ elements (MTJ element 300). FIG. 2 is the cross-sectional view showing the structure of an MTJ element 300 of the magnetic field writing type. The MTJ element 300 shown in FIG. 2 contains a nonmagnetic metal layer 204 whose both ends are a lower terminal n10 and a lower terminal n20, a free magnetic layer 203, a barrier layer 202 and a pinned magnetic layer 201. On the upper layer of the nonmagnetic metal layer 204, the free magnetic layer 203, the barrier layer 202 and the pinned magnetic layer 201 are laminated in turn, and the pinned magnetic layer 201 serves as an upper terminal n30. Here, the magnetization of the pinned magnetic layer 201 is fixed to an in-surface direction. In the MTJ element 300 shown in FIG. 2, the magnetization of only the free magnetic layer 203 is inverted by the magnetic field generated by the writing current flowing through the nonmagnetic metal layer 204, and the 1-bit information can be rewritten.
Another one example of the structure of the 3-terminal MTJ element will be described with reference to FIG. 3. FIG. 3 is the cross-sectional view showing the structure of the MTJ element 300 of the domain wall displacement type. The MTJ element 300 shown in FIG. 3 contains a hard magnetic layer 208a connected to the lower terminal n10, a hard magnetic layer 208b connected to the lower terminal n20, a free magnetic layer 207, a barrier layer 206 and a reference magnetic layer 205. The free magnetic layer 207 is laminated just on the hard magnetic layers 208a and 208b. Moreover, in the free magnetic layer 207, the reference magnetic layer 205 is laminated just on a region in which the hard magnetic layers 208a and 208b are not formed in a lower layer, with the barrier layer 206 between the free magnetic layer 207 and the reference magnetic layer 205, and the reference magnetic layer 205 serves as the upper terminal n30.
FIG. 3 shows a case in which all of the magnetic layers are magnetized vertically (z direction) with respect to the lamination surface. For example, in the hard magnetic layer 208a, the magnetization is fixed upwardly (the positive side of the z direction). In the hard magnetic layer 208b, the magnetization is fixed downwardly (the negative side of the z direction). Moreover, in the reference magnetic layer 205, the magnetization is fixed upwardly. In this case, in the free magnetic layer region just on the hard magnetic layer 208a, the magnetization is fixed upwardly, and in the free magnetic layer region just on the hard magnetic layer 208b, the magnetization is fixed downwardly, respectively. A free magnetic layer region in which the hard magnetic layers 208a and 208b are not formed in the lower layer of the free magnetic layer 207 is a region in which the magnetization is freely rewritten. For this reason, a domain wall is formed on any one side of the hard magnetic layers 208a and 208b. For example, in FIG. 2(b), the domain wall is formed at a vicinity of the hard magnetic layer 208a, and the magnetization state of the free magnetic layer region in which the hard magnetic layers 208a and 208b are not formed in the lower layer becomes downward. In this state, when a current is supplied to the orientation from the terminal n20 to n10, the action of a spin polarization current causes this domain wall to be displaced rightwardly (the positive side of the X direction) and stopped at a vicinity of the hard magnetic layer 208b. Consequently, the magnetization state of the free magnetic layer region in which the hard magnetic layers 208a and 208b are not formed in the lower layer is transited upwardly. Moreover, when the current is supplied to the orientation from the terminal n10 to n20, the action of the spin polarization current causes the domain wall to be displaced leftwardly (the negative side of the X direction) and stopped at a vicinity of the hard magnetic layer 208a. Consequently, the magnetization state of the free magnetic layer region in which the hard magnetic layers 208a and 208b are not formed in the lower layer is transited downwardly. With these operations, it is possible to rewrite the 1-bit information.
The memory cells 200 shown in FIGS. 1A and 1B are arranged in matrix, and an arrayed memory array is consequently formed. FIG. 4 is a circuit diagram showing the configuration of the memory array in which the memory cells 200 shown FIGS. 1A and 1B are arrayed in the matrix of 4 rows×3 columns. FIGS. 5A to 5C are the plan views showing the layout structure of the memory array shown in FIG. 4. FIGS. 5A to 5C show an example of plan views of the memory array formed by the memory cells 200 in which the MTJ elements 300 of the domain wall displacement type are used. FIG. 6 is an A-A′ cross-sectional view in FIGS. 5A to 5C.
In detail, FIG. 5A is the plan view showing the structure from the substrate to an MTJ element formation region just under the second interconnection layer M2. FIG. 5B is the plan view showing the structure from the second interconnection layer M2 to a contact formation region just under the third interconnection layer M3. FIG. 5C is the plan view showing the structure of the upper layer from the third interconnection layer.
With reference to FIGS. 5A to 5C and FIG. 6, a contact 210a and a metal interconnection 209a forming the lower terminal n10 are laminated in turn on an N+ diffusion layer 211a formed on the P-type substrate, and the hard layer 208a is formed on its upper layer. Also, a contact 210b and a metal interconnection 209b forming the lower terminal n20 are laminated in turn on an N+ diffusion layer 211b formed on the P-type substrate, and the hard layer 208b is formed on its upper layer. The free magnetic layer 207 is formed in the upper layer of the hard layers 208a and 208b, and the barrier layer 206 and the reference layer 205 are formed in the upper layer of the free magnetic layer 207 in which the hard magnetic layers 208a and 208b are not formed in the lower layer.
As exemplified in FIG. 5A, the ideal minimum area of the memory cell 200 that is minimized in a design rule is 12 F2, and the bit cost becomes 1.5 times as compared with the 1T1MTJ cell configuration. However, the 2T1MTJ cell configuration can solve the subject of the half-selection state as mentioned before and can reduce the interconnection current to 1 mA or less and can further simplify peripheral circuits. For this reason, the cell occupation rate in the MRAM can be increased similarly to the rate of the DRAM. As a result, it is suitable for attaining a larger capacity.
An MRAM that includes the MTJ element of the domain wall displacement type is described in, for example, Japanese Patent Application Publication JP2009-99625A (referred to as the patent literature 2) and Japanese Patent Application Publication JP2003-297069A (referred to as the patent literature 3). In the MRAM described in the patent literature 2, as shown in FIG. 4, in the transistors M100 and M200, their source electrodes are connected to the bit line 210 (BL) and the bit line 220 (/BL), respectively, their drain electrodes are connected to the two terminals n20 and n30, respectively, and the gate electrodes are commonly connected to the word line 230. Then, the currents IW and IS are controlled by the transistors M100 and M200. In the MRAM described in the patent literature 3, in the transistors M100 and M200, their source electrodes are connected to the bit lines 210 (BL) and 220 (/BL), respectively, and the drain electrodes are connected to the two terminals n20 and n30 in the MTJ element 300, respectively, and their gate electrodes are connected to the different two word lines 230, respectively. Then, the currents IW and IS are controlled by the transistors M100 and M200.
Also, WO2006/054588 describes an MRAM in which a longitudinal direction has a magnetization free layer of 45° with respect to the word line (referred to as the patent literature 4).